[an error occurred while processing this directive] [an error occurred while processing this directive] The U of Iowa's DEC PDP-8 Restoration [an error occurred while processing this directive] [an error occurred while processing this directive] [an error occurred while processing this directive]
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The University of Iowa's DEC PDP-8

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Restoration Log

[an error occurred while processing this directive] Part of [an error occurred while processing this directive] the UI-8 pages
[an error occurred while processing this directive] See also [an error occurred while processing this directive] (none)
[an error occurred while processing this directive] [an error occurred while processing this directive] (none) Douglas W. Jones [an error occurred while processing this directive] (none)
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THE UNIVERSITY OF IOWA Department of Computer Science [an error occurred while processing this directive] and (none) [an error occurred while processing this directive]

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Contents


Introduction

This is a chronological log of the progress restoring the University of Iowa's PDP-8 computer. Entries are added at the end as work progresses. Click on any thumbnail image to see full-sized image.


Feb 12, 2018, W034 Cable

Bug 4 and Bug 64: Given that quite a bit of the the CPU seems to be working, we began to investigate the memory. One of the first things we noticed was that the Maintenance Manual (Feb. 1966 Ed., pages 10-70 to 10-76) documents 7 W034 cables between the CPU and memory half backplanes, but there are only 6 present. The missing cable (page 10-76) would connect backplane slots PD02 and MD35. While we have not fully understood the signals that pass through the various cables, this makes it more pressing that we attempt to manufacture replacements for these cables.

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W034D cable connector
We began by taking additional photos of the board that serves as a connector on each end of the cable, supplementing the photo taken on May. 27, 2014. We took key dimensions from the specifications in the Digital Logic Handbook, 1967 Edition, page 225, and measured the others from the photos. The diagrams to the left show our results.

Having done this, we found that Vince Slyngstad has already done much of this. See his CAD Project Files, indexed under ./DEC/Wxxx/W034: Flexprint, 16 connections on "B" side 10 ohms on A2, B2. This includes photos, schematics and board layouts for the W034D, W034H, and W034X. The latter is a modern redesign, while the two former are historical DEC designs. We need to evaluate his modern design to see if it meets our requirements.


Feb 14, 2018, Disconnect mag tape interface

Bug 31: After poking around the ADC rack, we decided to remove the locally built magnetic tape drive interface from the ADC rack. Removal of this device interface is complicated by the fact that it is not daisy-chained into the I/O bus the way off-the-shelf device interfaces were done. Instead, wire-wrap wiring has been used to tap into the I/O bus connectors in the analog to digital converter backplane immediately above it. In addition, spare slots in that backplane have been used for a few additional logic boards and interface plugs needed for the tape drive.

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Using an unwrapping tool
The first step was to remove the wires that connected between the ADC and the tape-drive interface, using the unwrapping end of a standard wire-wrap tool. All of DEC's factory wiring and field-changes were done with 24-gauge wire, almost all of it with yellow insulation. The wires we removed were a mix yellow of 30-gauge wire (with a woefully inadequate number of wraps on each pin) and some red and blue 24-gauge wire. We documented every wire removed in the log book, using DEC's standard coordinate system:

Pin E12B refers to a pin on row E (counting from the top), slot 12 (counting from the left side of the wiring side of the backplane) pin E (as printed in white on the wiring side of the black connector blocks). The tape-drive interface was mostly in rows E and F, with wiring to a few spare slots in row D and one slot (used for a cable connector) in row C. We logged the wire color, source pin and destination pin for each wire we removed.

We also pulled the cables that connected the tape-drive control panel to slots in the backplane segments involved. The wires at one end of this cable were soldered to parts of the control panel, another end of this cable ended in cut-off wires that apparently went to the tape drive, while the third and forth ends of this cable went to card-edge connectors plugged into the backplane. At least one of these was almost certainly plugged into the wrong backplane slot, but we wrote on each card-edge connector the slot number into which it had been plugged.


Feb 21, 2018, Remove mag tape interface, memory sleuthing

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Removing rows E and F
Bug 31: We continued removing wires, documenting the removals in the log book, until we thought no wires remained between rows A though D and rows E and F of the top backplane section of the ADC rack, and then we unscrewed the mounting panel for rows E and F, only to find that one wire remained. It turns out that the power connections to rows E and F was done by wire-wrapped wires from rows C and D instead of using the faston connector tabs on the left side of the mounting panels.

With the final wire removed, we were able to pull the remains of the home-brew tape-drive interface from the rack. We believe that some boards on the lower right end of row D are also part of this home-brew interface. Wiring to those boards from rows E and F has been removed, but the local wiring on row D remains in place.

The home-made tape drive control panel directly below rows E and F had one remaining cable still connecting it to other parts of the rack. In this case, to a block of relays attached to a board cantelevered out from the back of the topmost panel on the back of the rack. We simply cut the wires from the cable to this block of relays. The colors of the cut wires should be sufficient to allow reversing this change, should someone want to do so. We will tag all removed parts to allow this.

Bug 64: We tracked down David Gesswein's photos of a table-top PDP-8 he restored. These photos of his show the cabling between the two half backplanes:

These photos clearly show only 6 cables, all from Px01 to Mx36 (for x from A to F). The photos do not show the 7th cable connecting PD02 to MD35. On Feb. 12, 2018 we had speculated that perhaps this missing cable was the cause of our memory problems. Apparently, this is not the case. It appears that this cable is not needed on machines with only 4K of memory. Therefore, cable replacement moves down on our list of prioritie, but remains there because of the decayed nature of the 6 cables we have.

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Current limiters
The Maintenance Manual (Feb. 1966 Ed., page 9-12) says that the first thing we need to do when checking the memory is to measure and adjust the read/write current and the inhibit current. These currents are to be measured at the wire from the current-determining resistor to the appropriate backplane module. Where are these resistors? The explanation of the memory operation given in Figure 4-4 on page 4-6 of the Maintenance Manual shows an 80&Ohm; "current determining resistor" in the circuit, but it doesn't say where to look for it.

Looking at the detailed drawings in the Maintenance Manual, BS-D-8M-0-12 X Axis Selection, BS-D-8M-0-13 Y Axis Selection and BS-D-AM-0-15 Sense Amps, Inhibit Drivers, and Memory Control all show the detailed locations of the boards involved and document the role of 80&Ohm; current limiting resistors, but they don't show where the resistors are. We found these resistors lurking on an aluminum heat sink behind the balun network boards on the front-side of the core stack. See photo. These are all 80&Ohm; 10W 1% precision resistors. We infer from the fact that two of them have small resistor capacitor networks serving as shunts that those two are the X and Y axis current limiters attached to the G209 modules, while the other 13 resistors each serve one of the G208 inhibit drivers (the 13th resistor is a spare on our system since we don't have the memory parity option.) Note that this little RC network isn't documented in the maintenance manual.

A second problem we will face is that the above-cited manual pages all refer to handwritten notes that should be on the label of our memory module. We have found no such notes. The Dalby Datormuseum has a photo of the label on their PDP-8 memory that gives a R/W (select) current of 325mA and an inhibit current of 305mA, so if we cannot find documentation for our machine, we at least know reasonable values for these currents.


Apr 4, 2018, Add test points to memory resistors

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Instrumented current limiters
Bug 64: As noted on Feb. 21, we need to measure the current through the 80Ω current limiting resistors in the inhibit and select circuits. The manual says to do this by carefully fishing one of the yellow wires from the resistors out of the backplane in order to attach a current probe to it. This is something appropriate to do one or twice in the life of a machine, but if we want to preserve this machine for the long haul, we don't want to repeatedly flex any of the backplane wiring.

An alternative way to measure the current through any of the 80Ω resistors is to simply measure the voltage across the resistor, but they are inaccessible behind the circuit boards holding the memory balun coils. To allow this method of measuring the current, we attached a set of 4 test points at an accessible location directly behind the plate on which the resistors are mounted and wired a pair of test points across one of the resistors limiting the select current and one limiting the inhibit current.


Apr 11, 2018, Calibrate scope

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Inhibit and R/W select currents
Bug 64: We set up the scope, powered from a DC supply so that it was floating relative to ground, using the methodology discussed on Dec. 16, 2014. This allowed us to take current measurements across the 80Ω current limiting resistors in the memory circuit, and then we observed the waveforms shown here. We had extreme difficulty getting the scope to trigger properly when operating at 1µsec/division, and the current magnitudes we measured were far too low.

The good news is that we got waveforms on both the R/W select and inhibit currents. The waveforms start when you hit the CONT (continue) switch on the front panel, and they stop when you hit HALT. This means that the key memory control signals from the CPU are reaching the memory. This is the first time we have confirmed this.

Checking the scope by using its internal calibration oscillator, we found that it was way out of calibration, so we spent the rest of the afternoon searching the scope manual for calibration instructions and then doing what we could to calibrate it using its internal calibration oscillator and a DC voltmeter. The scope was, in fact, way out of calibration. The internal 10V DC supply from which the scope derives all of its other voltages was under 8 volts. Adjusting this and then bringing everything else into balance seems to have made the scope trigger circuitry work much better.


Apr 18, 2018, Examine memory current waveforms

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Inhibit and R/W select currents
1µsec/div hoiz; 10v/div vertical
Bug 64: We measured the Inhibit current and R/W select current. This was a bit difficult because the scope's graticule illumination only works when the scope is running from AC power. Oblique illumination with flashlight worked as a poor substitute.

The Dalby Datormuseum photo of their their PDP-8 memory label that gives a R/W select current of 325mA and an inhibit current of 305mA, so the values we see are in the right ballpark.

Because this is core memory, each memory cycle consists of a read/erase subcycle where the contents of the addressed word are destructively read, followed by a write/restore subcycle where the data just read is returned. The inhibit line is only pulsed during a write/restore cycle, and then, only when the value written is zero. Since we are currently reading all zeros from memory on every cycle, the inhibit line is pulsed once per cycle. This looks right.

The R/W select lines are more complex. During the read/erase subcycle, the read select line should be pulsed, and during the write/restore subcycle, the write select line should be pulsed. These pulses are mixed by the balun networks on the G603 boards attached directly to the core memory module to produce a negative current pulse for the read/erase subcycle and a positive pulse for the write/restore subcycle. Both the read and write select lines in each pair share a single current limiting resistor, as shown in the Maintenance Manual (1965 ed, Figure 4-4, page 4-6). Thus, we should see two current pulses during each memory cycle, one for the read/erase subcycle, and one for the write/restore subcycle. We do see two pulses per subcycle, but they are strangely brief and they have different magnitudes! Something seems amiss.

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Inhibit logic signal
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Read and Write logic signals
1µsec/div hoiz; 1.0v/div vertical
We checked the logic levels on the Inhibit, Read and Write logic levels that are inputs to the R/W select drivers and Inhibit drivers. Comparing these signals with the information shown in the Maintenance Manual (1965 ed, Figure 4-5, page 4-11). The inhibit signal looks right (although the waveforms shown in the manual are shown inverted relative to the scope display). Read is indeed a longer pulse than write, explaining some of the assymetry of the combined waveform on the R/W select current. This does not explain the low amplitude of the current for the shorter of the two subcycles.

We used internal triggering for these measurements, so do not read any meaning into the phase differences on the scope displays.


Apr 25, 2018, Check power supply regulation

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Measuring supply ripple
Bug 64: One hypothesis to explan the large difference in quality of the inhibit and R/W select currents measured on Apr. 11 and Apr. 18 is that the R/W select power supply regulation is bad or that the resistance in the path from the R/W select supply to the memory is high. To examine this, we examined the ripple on the power supply outputs while the machine was running.

The photo shows our oscilloscope as used in these measurements. As mentioned on Dec. 16, 2014, the scope is set up for differential measurement, sitting on a dry wooden plank to isolate it from ground and running from an isolated DC supply. This is required because the inhibit and R/W select power supplies are not regulated relative to ground.

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Inhibit ripple at core and at supply
1µsec/div hoiz; 0.2v/div vertical
The inhibit current waveform measured on Apr. 18 looked reasonable, so we began by measuring the ripple on the inhibit supply under load. The left photo shows the approximately 0.25V ripple measured across the capacitor mounted directly behind the memory stack, while the right photo shows the approximately 0.2V ripple at the supply output (measured between the Faston terminals at the back of the supply). The 60 cycle AC ripple amplitude we measured on Dec. 16, 2014 was only 0.005V, invisible on the 0.

The high frequency component of the ripple measured at the supply output is almost certainly an artifact of the feedback delay in the regulator circuit, and it is noteworthy that this high frequency noise is invisible at the other end of the several feet of twisted pair between the power supply and memory. What we do see at the other end is a low-voltage echo of the supply current waveform we measured on Apr. 18. The relatively low resistance (or, at these frequencies, impedance) of the twisted pair translates the current waveform to the waveform we observed.

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R/W select ripple at core and at supply
1µsec/div hoiz; 0.2v/div vertical
The R/W select current waveform measured on Apr. 18 was not so good. Again, measured the ripple under load. The left photo shows the approximately 0.55V ripple measured across the Faston terminals on the base of the backplane. (The capacitor analogous to the one we used to measure the select current is inaccessible when the machine is running.) The right photo shows the approximately 0.35V ripple at the Faston terminals of the power supply.

As with the inhibit current, R/W select current ripple at the memory is higher aplitude and reflects the current waveform measured on Apr. 18. Unlike the case with the Inhibit current, however, we do not see the high frequency artifacts of the regulator circuitry at the power supply output, but just the same miniature version of the current waveform. This leads us to suspect that something in the R/W select supply is not working correctly.

Note that, when we reformed the power supply capacitors (Bug 10), we found, on Mar. 13, 2014, that C15 was bad, and on Mar. 27, 2014, we installed a replacement. C15 is the final (post regulator) filter capacitor for the inhibit supply, while its twin, C16, is the final filter capacitor for the R/W select supply. Both are nominally 980µF 75V electrolytic capacitors, although our replacement is labeled 1000µF. If C16 capacitor is bad, it would lead to poor power supply regulation, but we also need to consider the possibility that the series regulator transistors are bad or that one of the G808 boards that control them is bad.


May 2, 2018, Swapping regulators has no effect

Bug 64: To help rule out problems with the power supply regulation, we tried switching the power transistors Q1 and Q2 inside the power supply. These are big 2N3715 80V, 150W, 10A Silicon NPN transistors mounted on the power supply frame. Q1 regulates the Inhibit supply, Q2 regulates the R/W Select supply. See the power supply schematic in the Maintenance Manual (1965 ed, Drawing RS-C-708, page 10-8). Switching the transistors had no obvious effect on the ripple signal observed across the power supply output, although in switching the transistors, we did notice that one of the mounting screws for one transistor was not very tight. This could have added resistance to the current path.

We also tried switching the G808 regulator boards in the power supply. Given that the set point of each board is adjusted differently, we would not expect the machine to work with these boards switched, but we wanted to see if the quality of voltage regulation changed. It did not, so we switched the boards back.

Conclusion. The power supply electronics is not obviously bad.


Sep 13, 2018, Memory control signals

Read
MC16
pin J
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Strobe
MD20
pin N
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Inhibit
Any G209
Pin E
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Write
Any G209
pin D
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Mem Done
MF36
Pin 1
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Bug 64: We decided to measure the memory control waveforms discussed in the Figure 4-5 of the 1965 edition of the Maintenance Manual (page 4-11). All of the oscilloscope views shown here were taken with the same scope settings, DC coupled, 1 volt per vertical division, 1µs per horizontal division. They are shown in the same order as they are in Figure 4-5.

Note that the Drawing BS-D-8M-0-13 in the Maintenance Manual shows Read and Write with filled-in diamonds as arrow heads. According to Figure 10-1, this notation indicates a negative level signal, that is, one where true is indicated with a negative voltage. Drawing BS-D-8M-0-15 shows Inhibit as a negative level.

Two things look wrong here: First, the memory strobe amplitude looks too small. The scope shows a negative pulse with an amplitude of about 1.4V. The source of this signal is a B360 module. The 1967 Logic Handbook, page 122, says that the output is a 40ns negative pulse with an amplitude of 2.5 volts. Fortunately, the B360 board has been reverse engineered by Vince Slygstad. We must check if we are working with Rev C (7-65) or rev D (11-65), but he has produced schematics of both boards.

The second puzzle has to do with the Inhibit and Write signals. These should be very similar, and neither should be almost coincident with Read. Inhibit pulses should begin 50ns before Write and the two pulses should end as the Memory Done pulse begins. (Note that the scope traces for Read and Write are inverted relative to the signals shown in the maintenance manual because they are negative logic signals.) The strobe pulse does occur in the center of a 600ns read pulse, as expected, and the Write pulse is about 500ns wide, ending with the Memory Done pulse. Something seems wrong with Inhibit, since it does not end coincidently with Read.

Have we hooked the scope probe to the wrong signal or is it really bad? Reviewing the schematics, particularly Drawing BS-D-8M-0-13 in the Maintenance Manual shows that pin E of any G209 board is not Inhibit, it is Read. We made a mistake.


Sep 27, 2018, Memory Strobe questions

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We reverse engineered the B360 board that generates the Memory Strobe signal, labeling all of the parts with reference to the B360D schematic. Our board is a B360C, but the parts all match, so the board revision must have been an improved board layout, not a change to the parts. Having done this, we plugged the board into an extender card in backplane slot MD20. Before we used the scope to follow the Memory Strobe signal through this board, we checked the reference voltages produced by the various diode ladders. In reverse engineering the board, we assumed nominal 0.6 volt forward voltage drops on the diodes, but we measured 0.65, so the -2.4V reference level is closer to -02.6V and the -7.1V level is similarly offset.

We did not change the triggering or horizontal sweep rate on the scope from the settings on Sept. 13", so the timing in those scope traces is the same as the timings shown here. All of the scope traces shown below were made with the zero reference 2 divisions above the center of the screen.

Q4 base
1V/div
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The delay line on the B360 attenuates the signal, so the output of the delay line half of the board includes a two-transistor amplifer. The first scope trace shown on the left is the input to this amplifier, resting just under one volt, with negative pulses to zero volts.
Q3 base
1V/div
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The first transistor, Q4 is used as an emitter follower, so its output is about 0.6 volts lower than its input, with no change in amplitude (but able to drive considerably more current).
Pin L
1V/div
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The second transistor, Q3, is an inverter, directly coupled to pin L, the output of the delay-line half of the B360. This idles at a voltage set by the forward drop of 6 silicon diodes, nominally -3V, and is pulled up close to ground with each pulse.
Q1 collector
2V/div
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The second half of the B360 is a 2-transistor pulse amplifier using transformer coupling. The collector of Q1 drives the transformer T1 with a voltage swing on the order of 8 volts.
Q2 collector
2V/div
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The output of transformer T1 is connected from base to emitter on Q2, and the collector of Q2 drives the output transformer T2. Here, he amplitude is around 4 volts.
Pin N
1V/div
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Pins N and P are the outputs of transformer T2. Here, pin P is grounded, so the transformer inverts the pulses, producing standard DEC 50ns pulses from a resting voltage of zero with an amplitude of about 1.5 volts driving 12 parallel loads.

In sum, the B360 seems to be working, with no obvious explanation of the low amplitude of the output pulses other than the low impedance of the 12 sense amplifiers that it drives in parallel.

We have two obvious questions: First, is our scope calibration good? The DC voltages we measured with our multimeter on the various DC busses on the B360 don't match the mesaurements with the scope.

Second, the output of each sense amplifier is an and function of the strobe pulse and the pulse amplified from the sense winding of the core memory. If the timing of the delay line is wrong, nothing will get through.

Note added Oct. 4: All pulses shorter than 100ns should look undersized on this scope! The advertised bandwidth of the Tektronix 321 scope we are using is 5MHz. It's an analog scope, so it does show features faster than 500MHz, but they are attenuated. So, the waveforms above are close to what we should expect if the B360 board is working perfectly.


Nov 7, 2018, An R-Series logic probe

Bug 65: On July 2, 2015, we built some very simple logic probes for DEC's R-series logic. These have an LED that glows when the logic level is 0V, and is off at -3V. They work well for debuging static logic, but to continue debugging the machine, we need to examine fast pulses. This led us to design a more complex logic probe for fast pulse detection. In the end, this design was only a partial success, more on that later.
  schematic disgram  

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Assembled In use

The photos to the right shows the entire probe circuit assembled on a sliver of protoboard, and then assembled in the casing of an old highlighter. The highlighter case was prepared by removing the plug from the base (it pulls out if you get a good grip on it with needle-nose pliers), pulling out the dry felt that formerly held the ink, scraping off the markings on the barrel and then drilling holes to align with the S1 and D2. It was difficult to push the circuit board into place and then insert twists of old vinyl cable sheath behind ti to wedge it into place. It turned out to be impossible to disassemble the probe without breaking off the switch handle.

Originally, we built this probe with the one-shot set up to make a 1 second blink. This was way too long, so we rebuilt it for a 1/2 second blink, replacing the large capacitor shown in the photo with a much smaller one.

The test leads were terminated with female Molex connector pins insulated with 1/8 inch shrink tubing. These pins fit nicely on DEC's wire-wrap backplane pins.

In testing, we found that this probe could easily detect 400 ns pulses and that it could usually detect 100 ns pulses. Pulse polarity matters for 400 ns pulses; the probe only reliably detects the leading edge of the pulse, not the trailing edge. This is because the one-shot has a recovery time after a wrong-polarity pulse determined by the RC time constant of C2 and the unknown resistance of the protection network on the CMOS logic input in parallel with R3.

This probe is totally blind to standard DEC R-series 40 ns pulses. Initially, we thought that the problem was too high a resistor protecting U1a, so we reduced this to 5 K&Ohm;. This was not sufficient, so we went back to the datasheets for the 4011 quad nand gate and found that the advertised gate delay of this chip grows quite long as the supply voltage falls below 5 volts. In sum, this was the wrong chip to use for a logic probe designed for work on DEC R-series logic, although it is fast enough to be useful with some of the slower timing signals in our machine.

We have one minor complaint about the probe: The electronics needs to be shielded. As it is, just touching the case of the former highlighter will sometimes trigger the one-shot.


Nov 8, 2018, The data path to memory

Bug 64: We used two of the logic probes we built on July 2, 2015, plus the new probe we finished on Nov. 7, we traced the flow of data from the switch register (bit 11, the least significant bit) to the inhibit drivers.

The path is as follows:

We cannot look at the path from memory without a faster logic probe. All data transfers from memory are very (40 ns) DEC standard R-series pulses produced by the sense amplifier, which ands the memory strobe pulse with the data from memory to produce the pulse that carries data to the memory buffer register, directly setting each bit where a 1 should appear.